1. Field of the Invention
The present invention generally relates to a manufacturing method of a chip integrated substrate in which a semiconductor chip is integrated on a substrate.
2. Description of the Related Art
At present, a high performance electronic instrument using semiconductor devices such as semiconductor chips has been developed, and in a case where a semiconductor chip is mounted on a substrate, a high density mounting is required. In addition, a small-sized substrate with a reserved area on which the semiconductor chip is mounted is required.
In order to meet these requests, a so-called chip integrated substrate in which a semiconductor chip is embedded in a substrate has been proposed, and various structures for integrating the semiconductor chip on the substrate have been proposed.
For example, in a case where a chip integrated substrate is formed, wiring to be connected to the semiconductor chip must be formed. As a method to form the wiring on the semiconductor chip, for example, a method in which an insulation layer is formed on the semiconductor chip, multi-layer insulation layers are laminated if necessary, and the wiring is formed on the insulation layer, has been used widely.
In this case, for example, when the wiring is formed on the semiconductor chip, via wiring for penetrating the insulation layer must be formed; for example, via holes are formed by using a laser, and the via wirings are formed in the via holes. This method has been used (refer to Patent Document 1).
[Patent Document 1] Japanese Laid-Open Patent Application No. 2004-165277 (refer to paragraph 0051, FIG. 5)
However, when the via holes are formed in the insulation layer, a so-called de-smearing process being a later process after forming the via holes is required, that is, a chemical treatment process is needed; therefore, there are problems in that the processes become complex and the cost increases.
In addition, in a case where the chip integrated substrate is formed as a thin type, for example, bowing of the substrate occurs and there is a problem in that its manufacturing becomes difficult. For example, when thermo-hardening insulation layers are laminated on a semiconductor chip and a thermo-hardening process is applied to each of the insulation layers, stresses of the multi-layer insulation layers are accumulated; therefore, it is difficult to avoid a problem that the bowing of the substrate becomes large, and there is a limit to manufacturing a thin type substrate.